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2 Principle of Data Acquisition

ring is read, and used to determine the detection time. Times longer than the reference cycle

time are determined by counting the reference cycles.

Counter

Ring Oscillator

G1 G2 G3

Encoder

fine time coarse time

Input

Readout

Pulse

Fig. 2: Principle of a digital TDC. The time of the input pulse is derived from the location of a reference pulse

cycling within a ring oscillator

Compared with the TAC-ADC principle used in fast TCSPC devices [1, 2] a TDC delivers

coarser time-channels. A TDC can, however, be built at a lower price and with considerably

lower power consumption. More important, a large number of TDC channels can be synchro-

nised to obtain comparable photon times in a large number of recording channels.

DPC-230 Architecture

Absolute Timing

A general block diagram of the DPC-230 is shown in Fig. 3. The device has two TDC chips,

each of which contains eight TDC channels. Both TDC chips are synchronised via a common

clock oscillator. Both TDC chips can be operated either with 8 LVTTL (Low-Voltage TTL)

inputs or with two ECL (Emitter-Coupled Logic) inputs. The LVTTL inputs are compatible

with all commonly used single-photon avalanche photodiode (SPAD) detectors. The ECL

inputs are driven by constant-fraction discriminators (CFDs). The CFD inputs are compatible

with the output pulses of photomultiplier tubes (PMTs).

CFD

TDC Channel1

TDC Channel2

TDC Channel3

TDC Channel4

TDC Channel8

TDC Channel9

TDC Channel10

TDC Channel11

TDC Channel12

CFD

In 1

In 2

In 3

In 4

In 8

FIFO

Bus

Interface

LVTTL

PMT

In 9

In 10

In 11

In 12

In 16

LVTTL

PMT

FIFO

2 million events

TDC Chip 1

TDC Chip 2

TDC Channel16

Clock Generator

Fig. 3: General architecture of the DPC-230

1 2 3 4 5 6 7 8 9 10 11 12 13 ... 69 70

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